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PCIe Gen 5 switches target machine learning, hyperscale computing

Technology News |
By Jean-Pierre Joosting

To meet the demands of applications such as data analytics, autonomous-driving and medical diagnostics that are driving extraordinary demands for machine learning and hyperscale compute infrastructure, Microchip Technology has announced the first PCI Express (PCIe) 5.0 switches. The Switchtec PFX PCIe 5.0 family doubles the interconnect performance for dense compute, high speed networking and NVM Express® (NVMe®) storage. Together with the XpressConnect™ retimers, Microchip is the industry’s only supplier of both PCIe Gen 5 switches and PCIe Gen 5 retimer products, delivering a complete portfolio of PCIe Gen 5 infrastructure products with proven interoperability.

“Accelerators, graphic processing units (GPUs), central processing units (CPUs) and high-speed network adapters continue to drive the need for higher performance PCIe infrastructure. Microchip’s introduction of the world’s first PCIe 5.0 switch doubles the PCIe Gen 4 interconnect link rates to 32 GT/s to support the most demanding next-generation machine learning platforms,” said Andrew Dieckmann, associate vice president of marketing and applications engineering for Microchip’s data center solutions business unit. “Coupled with our XpressConnect family of PCIe 5.0 and Compute Express Link™ (CXL™) 1.1/2.0 retimers, Microchip offers the industry’s broadest portfolio of PCIe Gen 5 infrastructure solutions with the lowest latency and end-to-end interoperability.”


The Switchtec PFX PCIe 5.0 switch family comprises high density, high reliability switches supporting 28 lanes to 100 lanes and up to 48 non-transparent bridges (NTBs). Switchtec technology devices support high reliability capabilities, including hot-and surprise-plug as well as secure boot authentication. With PCIe 5.0 data rates of 32 GT/s, signal integrity and complex system topologies pose significant development and debug challenges.

To accelerate time-to-market, the Switchtec PFX PCIe 5.0 switch provides a comprehensive suite of debug and diagnostic features including sophisticated internal PCIe analyzers supporting Transaction Layer Packet (TLP) generation and analysis and on-chip non-obtrusive SerDes eye capture capabilities.

Rapid system bring-up and debug is further supported with ChipLink — an intuitive graphical user interface (GUI) based device configuration and topology viewer that provides full access to the PFX PCIe switch’s registers, counters, diagnostics and forensic capture capabilities.

“Intel’s upcoming Sapphire Rapids Xeon processors will implement PCI Express 5.0 and Compute Express Link running up to 32.0 GT/s to deliver the low-latency and high-bandwidth I/O our customers need to deploy,” said Dr. Debendra Das Sharma, Intel fellow and director of I/O technology and standards.

Microchip has released a full set of design-in collateral, reference designs, evaluation boards and tools to support customers building systems that take advantage of the high-bandwidth of PCIe 5.0.

The Switchtec PFX PCIe 5.0 family of switches are sampling now to qualified customers.

www.microchip.com


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