NXP launches MCUs, crossover processors on Cortex-M33
The Cortex-M33 is based on the ARMv8-M architecture, which is a real-time deterministic embedded processor and adds TrustZone security and stack limits to the previous architecture ARMv7-M.
Both families therefore improve security while supporting real-time operating systems such as RTOS. The RT600 series comes with some additional DSP features in support of machine learning and artificial intelligence applications at the edge, including far-field voice input and immersive 3D audio playback.
The RT600 series is manufactured using 28nm FDSOI and comes without an on-chip non-volatile memory option at present. The LPC5500 is implemented in an 40nm embedded flash process.
The two families include SRAM-based Physically Unclonable Function (PUF) technology licensed from Intrinsic-ID BV to provide an immutable hardware root-of-trust. Optionally, keys can be injected through a traditional fuse-based methodology.
The Cortex-M33 has a dedicated co-processor interface that allows integration of tightly-coupled co-processors while maintaining full ecosystem and toolchain compatibility. NXP has utilized this capability to implement a co-processor for accelerating machine learning and DSP functions, such as, convolution, correlation, matrix operations, transfer functions, and filtering. This can be used to enhance performance by as much as a factor of compared to executing on Cortex-M33.
The LPC5500 offers single- or dual core Cortex-M33 along with up to 640kbytes of flash and 320kbytes of SRAM. Volume production starts 1Q19 and devices within the LPC55S6x family start at $1.99 for 256kbyte flash and $2.49 for 640kbyte flash in 10,000-unit quantities.
The iMX.RT600 features an Cortex-M33 that can be clocked at up to 300MHz and 600MHz Cadence Tensilica HiFi 4 audio/voice digital signal processor (DSP) with four MACS and hardware-based transcendental and activation functions. It supports the cores with 4.5Mbytes of on-chip SRAM. The crossover processors include an audio/voice subsystem with support of up to eight digital microphone channels, with hardware for Voice Activation Detect (VAD), and up to eight I2S peripherals.
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