New RXv3 CPU core achieves 5.8 CoreMark/MHz
The MCUs have been designed for the real-time performance and enhanced stability required by motor control and industrial applications.
The RXv3 core offers high performance, with a 5.8 CoreMark/MHz, as measured by EEMBC Benchmarks, as well as power efficiency and responsiveness. The RXv3 core is also backwards compatible with the RXv2 and RXv1 CPU cores in Renesas’ current 32-bit RX MCU families. Binary compatibility using the same CPU core instruction sets ensures that applications written for the previous-generation RXv2 and RXv1 cores carry forward to the RXv3-based MCUs.
The new RXv3 CPU core is primarily a CISC architecture that provides high code density, and it also uses a pipeline to deliver high instructions per cycle (IPC) performance. The enhanced RX core five-stage superscalar architecture enables the pipeline to execute more instructions simultaneously while maintaining excellent power efficiency The RXv3 core will enable the first new RX600 MCUs to achieve 44.8 CoreMark/mA with an energy-saving cache design that reduces both access time and power consumption during on-chip flash memory reads, such as instruction fetch.