Everspin Technologies has announced engineering samples of its newest, high-density STT-MRAM, the EM128LX. This product supports the Expanded SPI (xSPI) standard protocol and has a capacity of 128 Mbits, twice that of the previously announced 64 Mbit EM064LX. The combination of increased density with up to 233 megabytes/second full read and write bandwidth means that system designers now have the option of merging code and data memory on the same device, reducing cost, power, and area. With ultra-fast write speed and data persistence, the EM128LX will provide FPGA system designers with extremely fast configuration, instant-on boot capability, and rapid updates of critical application parameters such as weighting tables in AI applications.
“Everspin is leading the way in the ability to unify memory functions in one chip while maintaining ease-of-use for system designers,” said Sanjeev Aggarwal, President and CEO of Everspin Technologies.
The EM128LX is offered in two industry standard package types, a 24-ball BGA and 8-pin DFN. Everspin’s advanced Spin-transfer Torque MRAM (STT-MRAM) provides over 10 years of data retention, virtually unlimited write cycle endurance, and comes complete with the xSPI interface that supports NOR Flash and serial SRAM operating modes.
“System designers using FPGAs will benefit from the fast configuration updates made possible with the write speed and density of this latest STT-MRAM offering,” said Allan Cantle, CEO of Nallasway Inc. “Getting to Octal xSPI and 128 Mbit capacity enables shorter development times for a wide range of commercial FPGA families.”
The new JEDEC xSPI standard is expected to become the most prevalent way to access data memory and code storage in embedded systems.
Customer samples are available for shipment now, volume production shipments of the EM128LX will start in the early part of 2023.
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