Leti details new memory design that shrinks SRAMs by 30%

Leti details new memory design that shrinks SRAMs by 30%

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Leti has published a new paper titled “Advanced Memory Solutions for Emerging Circuits and Systems” that the company initially presented at IEDM 2017. The paper details how Leti combined FD-SOI technology with its 3D CoolCube monolithic stacking technology to create 4T SRAM bitcells with the same functionality level of 6T bitcells, reducing the memory footprint by 30 percent. 
By eeNews Europe


Another memory design breakthrough detailed in the paper include an embedded Content-Addressable Memory (CAM) dynamically configurable into a Static Random-Access Memory (SRAM) depending on the application running on the SoC.

1) ReCAM organization.

Leti proposes a high-speed 6T-ReCAM/SRAM (Reconfigurable CAM/SRAM) compatible with compact 6T SRAM foundry bitcells, with the CAM and SRAM words orthogonal to each other. Fabricating an 8Kb test-macro in 28nm FD-SOI technology, the authors highlight that their reconfigurable CAM/SRAM outperforms the state of the art, with operations clocked at 1.56GHz (at 0.9V), drawing as little as 0.13fJ/bit energy per search.

TFET DRAM bitcell storing logical ‘0’ and ‘1’.
TFET DRAM bitcell storing logical ‘0’ and ‘1’.

On another front, Leti explored the use of advanced Tunnel Field-Effect Transistors (TFET) for the design of a 1T1C refresh-free DRAM and a 2T1C SRAM. The core of these two circuits consists in a reverse-biased (drain-to-source) TFET and a capacitor see figures 2 and 3. Compared to the state of the art, the proposed bitcells show similar density, lower capacitance value, competitive latency and a significantly improved leakage (orders of magnitude lower at under 1fA/bit), note the authors.

“Enabling TFET-based DRAM and integrating TFET standard cells into CMOS designs will allow circuit designers to take advantage of the best features of both technologies”, explained Bastien Giraud, lead author of the paper.

In the same paper, Leti also proposed a novel compensation technique for crosspoint memory that reduces the voltage drop and leads to larger memory arrays, while reducing the impact of temporal and spatial variations.

To mitigate the voltage drop impact on large arrays, Leti proposes a compensation circuit that can be inserted between the controller and write circuitry, allowing the programing voltage to be shifted (positively or negatively) according to the location of the accessed bitcell, directly linked with its address.

“If this written bitcell is located in a sector close to the write circuit (with a limited resistive path), a small voltage drop is observed, leading to a negative voltage shift to minimize the stress due to over programing step. On the contrary, a positive shift is applied when the sector is far away from the write circuitries. This compensation system is compatible with multi-level crosspoint”, reads the paper. The compensation can be dynamically adjusted when too many fails occur on the same memory sector due, for example, to time-induced and environment variations.

Leti – www.leti-cea.fr

Related articles:

Coolcube circuit stacking moves to FinFET process

Monolithic 3D integration beats next node

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