IP builds optimised single-port RAM in TSMC 28 nm process

For IoT applications requiring ultra low-power solutions to extend battery life-time for wireless-connected devices, SoC architects optimize power modes by partitioning the SoC. This minimizes dynamic power in active modes, as well as power leakage in stand-by modes. To assist theis process, Dolphin Integration offers its Calypso architecture, a Single-port SRAM is designed to optimize power consumption, with gains between 20 and 30% compared to alternative solutions in 28 nm.

The SpRAM Calypso improves performance thanks to its data retention mode, with a memory core lowered to 0.63V. This minimum voltage retention feature allows leakage to be divided by between 2 and 10 (depending on memory size) compared to other memory compilers in stand-by mode. SpRAM Calypso is part of a Dolphin’s 28 nm HPM portfolio, which includes:

– ultra high-density 6-track standard cell libraries,

– a unique cache controller, R-Stratus-LP, both improving speed and reducing power consumption by up to 3 times, compared to stand-alone eFlash memory,

– MAESTRO, a fabric IP making the implementation of the Activity Control Unit of a low-power SoC easy and safe.

Dolphin Integration; www.dolphin-integration.com