Imec & Cadence tapeout first test chip for 5-nm technologies

Imec & Cadence tapeout first test chip for 5-nm technologies
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Nano-electronics research centre imec (Leuven, Belgium) and Cadence Design Systems, have announced first tapeout of a 5nm test chip using extreme ultraviolet (EUV) as well as 193 immersion (193i) lithography.
By eeNews Europe


Development of EUV technology has been a major programme at imec over several years (using light of sufficiently short wavelength to enable direct imaging of patterns at nanometre dimensions). To produce this test pattern, imec and Cadence say they optimised design rules, libraries and place-and-route technology to obtain optimal power, performance and area (PPA) scaling using Cadence’s Innovus Implementation System. The geometry came from a processor design, although the exercise was – at this stage – concerned with demonstrating that patterns of the appropriate size could be defined to be laid down on silicon. In parallel with EUV effort imec and Cadence taped out designs using Self-Aligned Quadruple Patterning (SAQP) for 193i lithography, where metal pitches were scaled from the nominal 32nm pitch down to 24nm to push the limit of patterning. (Multiple patterning uses interference and diffraction to form images with dimensions smaller than that otherwise possible with light of a given wavelength – in this case, 193 nm. Whereas a conventional pattern mask will produce a ‘fuzzy’ image, multiple patterning ‘back-calculates’ the effect of interference and diffraction to pre-distort the mask image. Combining several such fuzzy images – in this case, four – can produce the required outcome despite the wavelength/dimension disparity.)

The definition of a metal pitch of 24 nm enables what foundries may, depending on the conventions they are following, choose to call “5 nm” technology. This announcement is concerned with the tape-out, that is, demonstrating that the geometric data for such a step can be generated. Vassilios Gerousis, Distinguished Engineer, Cadence and Praveen Raghavan, Principal Engineer, imec, add that, going forward, “There are three options we plan to expose: 1.) SAQP for the lines with 193i for the cuts and via (multi exposure); 2.) SAQP for the lines with EUV for the cuts and via (single exposure); and 3.) EUV for the lines and vias (no cuts needed).”

They note that there are no actual devices in the tapeout, “The objective of the tape-out is patterning, etch, lithography, metallisation, power-performance, process window and rule set learning… the ‘vehicle’ is metal layers, M2-via-M3.” [Metal layer 2/via/Metal layer 3.]

“However, during the place and route with Innovus, a full processor was taken with the device model, parasitics and timing closure. On the chip both the processor and SRAM were placed. The tapeout however [consists of] only M2-via-M3.

Innovus is Cadence’s next-generation physical implementation system, using a massively parallel architecture with advanced optimisation technologies. “Our collaboration with Cadence plays an important part in the development of the world’s most advanced geometries including 5nm and below,” said An Steegen, senior vice president of Process Technology at imec. “Together, we developed the necessary technology to enable tapeouts for advanced technology nodes such as this test chip.”

EDN Europe asked the team, “Do the results give encouragement that the effort to reach these geometries will be worthwhile?”

Vassilios Gerousis and Praveen Raghavan responded; “Absolutely! Initial simulation studies of lithography and etch surely shows that we can go down to 24nm pitch… the space of options is large and we are trying to explore this space…

“We do know that 193i SAQP could be pushed towards 20 nm pitch, in theory. So surely scalability can sustain further down to 5nm and more. However for this we need tighter collaboration across the value chain from design houses, EDA, research consortiums, foundries and equipment vendors. This was a clear demonstration of collaboration between imec/research consortium and a leading EDA vendor/cadence to speed up the scaling towards 5nm.”



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