Generate PAM4 signals for receiver compliance testing
PAM4, with its four-level signal modulation—compared to two-level signal modulation (PAM2), most commonly referred to as NRZ—avoids the signal degradation caused by the increased bandwidth. PAM4 succeeds by transmitting two bits per symbol. For a given data rate, it cuts the bandwidth in half as opposed to NRZ. For example, a 56 Gbit/sec PAM4 signal runs at 28 Gbaud/sec compared to a 56 Gbit/sec NRZ signal that runs at 56 Gbaud/sec. Here, we need to distinguish the symbol rate (referred to as the baud rate) from the data rate to make the comparison. Figure 1 shows the difference between PAM4 and NRZ signals.
Figure 1. PAM4 modulation (right) uses four amplitude levels and thus can transmit two bits per symbol as where NRZ (PAM2) sends one bit per symbol.
While a PAM4 signal experiences more ISI (intersymbol interference) than a PAM2 signal at a given baud rate, it experiences much less at a given data rate. That’s because PAM4 sends two bits per baud. This minimization of ISI at a given data rate on bandwidth-limited channels such as electrical backplanes is the main motivation for the switch to PAM4.
Generate PAM4 test signals
Figure 2 shows block diagram of a test setup that can generate differential PAM4 signalling. It uses two serial digital-pattern generators, two active programmable pre(de)-emphasis amplifiers, two passive microwave combiners, and two phase-matched cables after the combiners.
Figure 2. Block Diagram of PAM4 signal generator setup shows the differential output needed to drive a receiver.
To generate a PAM4 test signal, we designate one of the pattern generator/active amplifier pairs as the MSB, which provides an output amplitude twice as large as that from the other pair (designated as LSB). The resulting signal will meet all the electrical PAM4 signalling and transmitter performance parameters as specified in the standards for different symbol/data rates. Figure 3 shows the physical setup diagrammed on Fig. 2.
Figure 3. The direct connection between the test-setup components minimizes signal loss.
The use of two serial pattern generators lets us combine two uncorrelated data signals together, providing the flexibility to separately program the data patterns for the MSB and LSB. The active programmable pre(de)-emphasis amplifiers provide an easy way to introduce required (for PAM4 receiver testing purposes) signal alterations to both the MSB and LSB. The passive combiners are a straightforward way to generate a PAM4 signal from two input serial data sources. Here are some of the tests you need to perform.
Tolerance to jitter and noise
With four separate symbol levels to ascertain, PAM4 receivers must tolerate poor (compared to PAM2) signal-to-noise ratios and small symbol-to-symbol voltage swings. The amplitude of each eye in a PAM4 signal is roughly one-third that of an NRZ signal. An easy method to judge a receiver’s sensitivity is to lower the input signal amplitude until the BER (bit-error rate) reaches an unacceptable level. You can accomplish that by properly reducing the output amplitudes of both active amplifiers in parallel.
You can also achieve eye closure by using the pre(de)-emphasis of the active amplifiers to introduce ISI-type characteristics. The amplifiers can model a full passive frequency-dependent loss profile, thus removing the need to have any physical reference channels (e.g. compliance test boards) or programmable attenuators on hand.
Additionally, SJ (sinusoidal jitter) can be added to one or both of the bits of the PAM4 test signal to further decrease the eye opening. Figure 4 shows a 25 Gbit/sec PAM4 signal without any added SJ. Figure 5 shows 0.2 UI (unit interval) of SJ at 10 MHz added to both the MSB and LSB simultaneously.
Figure 4. A 25Gbit/sec PAM4 signal with no added SJ shows relatively clean eyes.
Figure 5. 25 Gbit/sec PAM4 signal with 0.2 UI of added SJ at 10 MHz shows smaller eye openings that seen in Fig. 4.
You also need to measure a receiver’s sensitivity to input signal linearity and level separation mismatch. To make those measurements, you should adjust all three PAM4 eye diagram heights together or separately as desired using the amplifiers’ output amplitude adjustments.
Additional receiver tests
An essential test for a receiver’s clock recovery circuit consists of evaluating its tolerance to various degrees of SJ over a certain frequency range. The degree of SJ at each frequency is specified in the jitter tolerance mask given by the standards. In general, PAM4 receivers must tolerate both several UIs of SJ (between 5 UI and 0.05 UI) at SJ frequencies below the clock recovery bandwidth and limited UI SJ (0.05 UI) for SJ frequencies above the clock recovery bandwidth.
A receiver’s equalization capability (CTLE and/or DFE) can be tested by subjecting it to the maximum ISI of any realistic transmitter and channel pairing. As stated earlier, ISI type effects can be generated using the pre(de)-emphasis capabilities of the active amplifiers.
PAM4’s present day and future standards do and will require separate compliance tests for cases of high interference/crosstalk with low ISI/insertion loss and low interference/crosstalk with high ISI and insertion loss. This makes sense because a receiver’s tolerance to interference and crosstalk can vary in different situations and thus separate tests are necessary. Again, the active amplifiers can use their individual amplitude control, pre(de)-emphasis, and jitter insertion capabilities to help create the required testing conditions. Further alterations of these elements can be used to gauge the receiver’s performance beyond the mandatory test conditions.
Using two signal generators, two amplifiers, and two mixers, you can build a test setup that exercises PAM4 receives for tolerance to jitter and to different eye heights. Changing these conditions lets you characterize the receiver and perform compliance tests.
Alexander Katsman is with ADSANTEC (ADSANTEC Corporation is a California-based high-speed mixed signal IC design house that specialises in providing cutting-edge custom built ASICs for the test and measurement, telecommunication, and computing markets.) Alexander is a UCLA graduate. He has been on the ADSANTEC team from 2008-2010 and rejoined the team at the end of 2015. At ADSANTEC, Alexander is in charge of Business Development and Marketing, helping spread knowledge of ADSANTEC’s High-Speed / High Frequency Product Lines.