Design software update for Altera’s high-capacity programmables
Areas that are uprated include compile time, versatile design entry methods and simplified intellectual property (IP) integration. The Quartus Prime Pro software v16.0 delivers a design methodology that is optimized for large designs with more than one million logic elements, and also adds an incremental optimization feature to reduce design iterations and accelerate timing closure.
A production release of Quartus Prime Pro Edition with hierarchical databases targets the next generation of high capacity, highly integrated FPGAs.
A production release of BluePrint platform designer reduces design iterations by a claimed factor of 10x by allowing designers to make pin assignments and clock planning early in their design.
The Qsys Pro system integration tool with a hierarchical framework supports multiple design entry formats and simplifies IP integration.
Incremental optimization support is intended to reduce design iterations.
There is also partial reconfiguration support for Arria 10 FPGAs & SoCs.
The Quartus Prime design software provides users access to an expanding selection of IP cores. These IP cores, in combination with numerous IP usability enhancements, help to improve designer productivity by simplifying IP evaluation, IP selection and hardware verification. Ethernet, Hybrid Memory Cube memory and Video IP cores extend the suite of high-performance, low-latency IP cores for industry-standard protocols.
The production release of the Quartus Prime design software v16.0 is now available for download at Altera’s eStore. The software is available in three editions (Pro, Standard and Lite), depending on target FPGA. The Quartus Prime Pro and Quartus Prime Standard editions come with the ModelSim-Altera Starter edition software and a full licence to the IP Base Suite. The annual software license is $3,995 for a node-locked PC license for the Quartus Prime Pro Edition; Quartus Prime Lite edition is available as a free download at Altera’s eStore.