Denali 3.0 image signal processor IP

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By Ally Winning

The camera-ready, end-to-end HDR ISP uses proprietary advanced algorithms to accurately tone map high contrast scenes for mission-critical applications.

Denali 3.0 has been redesigned for more efficient power consumption and better performance with an expanded 20-bit image processing pipeline and limited latency to less than 20 lines. The improvement in performance requires no external DRAM or frame buffers. Denali 3.0 provides best-in-class image quality for applications demanding native support of real-time high dynamic range video.

“As designers continue to expand sensor-based safety mechanisms for ADAS and autonomous robotic applications, the need for ultra-low latency, and high-quality visual data advances at every stage; with Denali 3.0, we are providing the building blocks for the future of these technologies,” said Alfred Zee, CEO of Pinnacle Imaging Systems. “The opportunity to collaborate with industry leaders like Xilinx, Inc. and ON Semiconductor has afforded us a unique opportunity to build on our high dynamic range ISP and meet the demands of next generation platforms that will service applications of the future.”

The Denali 3.0 ISP cores have been adapted from Pinnacle Imaging’s patented HDR technology. The technology is modelled on true human vision, enabling retention of local image contrast as well as details in highlights and shadows without producing halos or colour shifts. The fully programmable ISP offers a great del of flexibility. Denali 3.0 is also adaptable to support sensors of any resolution, non-traditional colour filter arrays (CFAs) and diverse HDR capture methods. Denali 3.0 runs exclusively on FPGA fabric, allowing the freeing up of on-chip CPU and GPU resources.

“A high-performance HDR ISP is critical in today’s numerous AI vision applications,” said Chetan Khona, Director, Industrial, Vision, Healthcare & Sciences at Xilinx. “The quality of any computer vision system’s results are only as good as the input data provided. We are thrilled that Pinnacle has successfully ported their Denali 3.0 ISP to our Zynq UltraScale+ family of MPSoCs, providing an adaptive ISP to meet our customers’ needs for mission-critical applications.”

Denali 3.0 supports the full line-up of Xilinx Zynq 7000 series and Zynq UltraScale+ programmable SoCs. It has native support for the ON Semiconductor AR0233 with a 20-bit image processing pipeline in Super Exposure Mode producing 120dB (20EV) of dynamic range with LED flicker mitigation.

“Achieving world-class dynamic range is a key focus for ON Semiconductor automotive sensor solutions. Our Hayabusa family of sensors are designed to achieve maximum dynamic range with LED flicker mitigation (LFM). Pinnacle Imaging Systems is on the-cutting edge of HDR processing technology, adapting its flexible ISP to support our new sensor innovations.” said Stephen Harris Director of Automotive Solutions Architecture for ON Semiconductor’s Automotive Sensing Division. “Their programmable Denali 3.0 ISP expands their data processing pipe to support the Hayabusa family’s native super-exposure 20-bit output achieving highest possible dynamic range with LFM.”

Several configurations of Denali 3.0 are already available for deployment on Xilinx Zynq 7000 and Xilinx Zynq UltraScale + Programmable SOC platforms as well as ON Semiconductor AR0233 and AR0239 configurations. Pinnacle will also deliver fully-customizable IP blocks for ASIC or system-level implementations with additional sensors to be supported soon.

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