CSEM/Fujitsu collaboration on ultra-low-power process
The agreement covers the development of ultra-low voltage, ultra-low power standard cell libraries, power management cells and memories as well as the development of a representative qualification vehicle to showcase the technology, and will include cross-licensing of related IP.
In areas such as wearable and IOT devices the requirements of increased miniaturization along with longer battery life mean that standard CMOS technologies are reaching their limits and that new solutions are urgently needed. Since, the two companies confirm, the power consumption of digital circuits is proportional to the square of the supply voltage, “low voltage operation is the best hope for significant improvements while maintaining NRE costs in check.”
MIFS’ Deeply Depleted Channel (DDC) technology enables fabrication of extremely-low-leakage transistors operating at supply voltages (Vdd) below 0.5V to obtain maximum power efficiency. DDC offers a better Vt mismatch and spread than conventional CMOS, allowing lower Vdd with minimum degradation of performance. Applying DDC to 40/55 nm CMOS along with mixed signal/RF and embedded NVM (non-volatile memory) allows cost-effective and highly integrated analogue and RF SoCs for IoT /wearable platforms. CSEM has long-established design experience in low-voltage, low-power integrated circuits, and the partnership intends to develop an ultra-low power IP platform targeting near/sub-threshold supply voltages in the MIFS DDC technology. The goal is to develop a best-in-class Extreme-Low Power (ELP) platform with the associated ecosystem to enable chip designs for energy-critical wearable and IOT devices.
The development will be performed in close direct collaboration between process engineers, library specialists and ULP design experts, both in Japan and Europe, to maximise the potential of the new platform, which is expected to be available for limited release in Q4 2016.
MIE Fujitsu Semiconductor (MIFS); www.fujitsu.com/jp/group/mifs/en/