Cadence smooths flow from silicon to package to PCB
The motif of the problem of “handing a design over the wall” from one design discipline to another, and the issues that result, has been a familiar theme in EDA. This time around, Cadence has identified the sequence of connectivity designs from the IC itself through to the PCB, as requiring an upgrade. The intent is that IC I/O should be finalised in the context of the optimum package layout; and the package layout in the context of the PCB; and all to optimise overall performance and signal integrity. As well as physical layout parameters, the flow can feed “real” (extracted) electrical parameters forward and back so that simulated circuit performance can take account of actual layout.
Cadence’s offering therefore aspires to a “seamless design flow between IC, package and board” and integrates the Virtuoso platform with Allegro and Sigrity technologies to streamline overall design process and significantly improve productivity and cycle time. The Virtuoso System Design Platform, is a formal, streamlined and automated co-design and verification flow between the Cadence Virtuoso platform and Allegro and Sigrity technologies. (Formal in this case meaning, a recognised, structured path between the tools, rather than the ‘formal verification’ sense of the term.) This higher level of integration enables engineers to design concurrently across the chip, package and board. By automating what has until now been a manual process, the Virtuoso System Design Platform minimizes errors and can reduce layout versus schematic (LVS) time between IC and package from days to minutes.
Engineers, Cadence says, are having to integrate multiple “heterogeneous technologies” in a single product, affecting the performance and functionality of ICs and introducing a new set of challenges for semiconductor companies. This cross-platform solution is therefore intended to streamline and automate the design of a package or module featuring off-chip devices and multiple ICs based on differing process design kits (PDKs).
The Virtuoso System Design Platform allows IC designers to easily include system-level layout parasitics in the IC verification flow, enabling time savings by combining package/board layout connectivity data with the IC layout parasitic electrical model. The resulting automatically generated “system-aware” schematic can then be easily used to create a testbench for final circuit-level simulation. Until now, designers were only able to make changes after time-consuming manual checks involving spreadsheets and other ad hoc/manual methods, which can take days. By automating this entire flow, the Virtuoso System Design Platform eliminates the highly manual and error-prone process of integrating system-level layout parasitic models back into the IC designer’s flow, reducing days of work to minutes.
“With the increasing complexity of today’s chips, packages and boards, designing each in isolation is no longer feasible,” said Tom Beckley, senior vice president and general manager of the Custom IC & PCB Group at Cadence. “…our customers can reduce risk and get to market faster with optimized designs featuring multiple heterogeneous ICs, including RF, analogue and digital devices.”