Aldec strengthens support for VHDL and UVVM

Aldec strengthens support for VHDL and UVVM

Aldec has improved its Riviera-PRO functional verification platform to add features to VHDL-2018 and Universal VHDL Verification Methodology (UVVM) 2019.09.02 version.
By eeNews Europe


Riviera-PRO 2019.10 users can now access newer attributes and improvements in the existing implementations of VHDL-2018, such as the to_string function and ‘IMAGE attribute can now be applied to all composite types that are representable.

The 2019.09.02 release of UVVM will feature new config to deassert tvalid once or multiple random times in AXI-Stream BFM and the ability to deassert tready multiple random times in AXI-Stream BFM.

Riviera-PRO’s Register Generator has also been enhanced to support FIFOs, indirect registers and arrays of registers.

More information

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