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Xilinx promises revolutionary architecture at 7nm

Xilinx promises revolutionary architecture at 7nm

Technology News |
By eeNews Europe



At a pre-launch event held in London, recently elected CEO Victor Peng justified the need for the new architecture as a way to circumvent the demise of Moore’s law, considering the ACAP as the mother of all future ASICs.

“It’s not that we don’t know how to go to the next node, but the economics of Moore’s law have stopped working. Getting better performance or faster devices for cheaper is no longer true”, the CEO said. This was hinting at the fact that for ASIC designers, it is becoming increasingly difficult to find the volumes that would justify the fixed value of an ASIC, without the possibility to optimize it for a wide mix of applications. 

“The speed of innovation is outpacing silicon design cycles, and what do you do about this challenge?” Peng asked the audience, highlighting the need for adaptable chips.

The ACAP was presented as a major technology disruption for the industry, and Xilinx’s most significant engineering accomplishment since the invention of the FPGA, no less. At its core, the ACAP has a new generation of FPGA fabric with distributed memory and hardware-programmable DSP blocks, a multicore SoC, and one or more software programmable, yet hardware adaptable, compute engines, all connected through a network on chip (NoC). Peng would remain evasive regarding the actual blend of fabric. “The way we create the bitstream is completely different, and the NoC enables above GHz flow control” the CEO said later during an interview with eeNews Europe.

The ACAP also has highly integrated programmable I/O functionality, ranging from integrated hardware programmable memory controllers, advanced SerDes technology and leading edge RF-ADC/DACs, to integrated High Bandwidth Memory (HBM) depending on the device variant. What makes it adaptive is that it can be changed at the hardware level to adapt to the needs of a wide range of applications and workloads, dynamically during operation.


This in order to deliver levels of performance orders of magnitude better than today’s CPUs, while being adaptable to more use cases than GPUs or ASICs. But haven’t we heard that on-the-fly reconfigurability story before and what is different this time? The ACAP would adapt to multiple workloads on the same piece of silicon, with reconfigurable engines within a novel type of fabric (itself reconfigurable?)

Could Xilinx be borrowing some of the new fabric elements from FPGA startup Efinix? The Californian startup claims a 4x power-performance-area advantage over traditional programmable technologies thanks to the use of blocks that can be configured for routing or logic depending on the circuit being implemented. In September last year, Efinix announced a $9.5M funding round led by Xilinx, bringing its total raised funds to circa $16.5M.

Does that make Xilinx a majority investor and does it give Xilinx some control power over Efinix’ roadmap? “All we can confirm is that we have invested in Efinix” was a rather short answer.

Discussing the Effinix investment and various other startups offering to embed FPGA fabrics into ASICs, Peng said that although embedded FPGA was not considered as a prominent innovation strategy for Xilinx, the company could enable it, and if it became strategic, then an acquisition could make sense. But for now, Xilinx has merely established a partnership with Effinix who uses Xilinx’s tools and coding ecosystem.

“Embedded FPGA doesn’t keep me awake at night” the CEO said jokingly, considering this technology segment as negligible competition for a company that expects most of its revenues from high-end FPGAs.


A block diagram of the ACAP-based Everest.

Going back to the ACAP architecture, it is aimed at a broad set of applications in the emerging era of big data and artificial intelligence and software and hardware developers will be able to design ACAP-based products for end point, edge and cloud applications. Working on physical implementation, Peng revealed that the first ACAP product family, codenamed “Everest,” would be developed in TSMC 7nm process technology, due to tape out later this year, boasting 50 billion transistors and the result of over one billion dollars of R&D spending.

With this new product line, Xilinx aims to make data centres its priority growth segment, while also accelerating growth in its core markets and taking the lead in what it sees as an emerging adaptive computing era.

Software developers will be able to target ACAP-based systems using tools like C/C++, OpenCL and Python. An ACAP can also be programmable at the RTL level using FPGA tools and Xilinx stated that over 1,500 hardware and software engineers were currently designing “ACAP and Everest” at the company. Software tools have been delivered to key customers. As for performance comparisons, “Everest” is expected to achieve 20x performance improvement on deep neural networks compared to today’s latest 16nm Virtex VU9P FPGA and “Everest”-based 5G remote radio heads will have 4x the bandwidth versus the latest 16nm-based radios.

Xilinx – www.xilinx.com

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CEO change at Xilinx: former COO Victor Peng to replace retiring Moshe Gavrielov

FPGA startup delivers first product

Xilinx’ Zynq ultrascale+ RFSoC chips integrate the RF signal chain

FPGA startup wins funds from Xilinx, Samsung

Xilinx expands ecosystem around Zync MPSoC

 

Captions

2) Xilinx’s CEO Victor Peng presenting the Adaptive Compute Acceleration Platform (ACAP).

 

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