However, the appropriate implementation of TSN is still a major technical challenge. In classical Ethernet, when a network node sends a data packet "A", it must complete its transmission before sending another data packet. It becomes difficult when another, but more urgent, packet "B" suddenly moves to the top of the queue, because otherwise it would miss a deadline. The sender must wait for the transmission of packet A to complete - or abort it, send packet B first, and then resend the entire packet A. The sender must then wait for packet "B" to complete its transmission. The (undesirable) result: The effective bandwidth is limited to minimize latency.
In TSN-enabled networks, however, the sending node can effectively pause packet A during transmission, transmit packet B first, and then continue with packet A where it interrupted it. Even with relatively slow networks (100 Mb/s), the controller has less than 82 µs to evaluate all queuing options and decide how best to proceed. At gigabit speeds, this time window is reduced to 8 µs.
The implementation of TSN thus requires a combination of microprocessors and the specific decision making capabilities of FPGAs. Xilinx is therefore working closely with two groups involved in this process - the AVnu Alliance and the Industrial Internet Consortium - who have been working on TSN for several years. Xilinx already demonstrated key industrial protocols such as OPC UA, DDS and EtherCAT based on TSN at SPS IPC Drives 2016 in Nuremberg, Germany.
In 2017, Xilinx released a preliminary version of its own TSN support under the title "1G/100M TSN Subsystem LogiCORE IP". It works with the Xilinx Zynq-7000 or Zynq UltraScale+ MPSoC devices and provides single-chip solutions for a variety of applications. At SPS IPC Drives 2018, Xilinx demonstrated a MARA Collaborative Robot (Cobot) from Acutronic Robotics that critically depends on real-time control of its speed, accuracy and safety. Xilinx's Zynq-based TSN solution enables Ethernet-based communication as used in multi-axis cobots.
Other customers with early access to Xilinx products have also achieved promising results. General Electric, for example, comments: "In our internal testing, the Xilinx IP core has met some of our most stringent requirements. In terms of performance, we measured a variation in packet delay of less than 50 ns (peak-to-peak). We found that the Xilinx IP core extensively met TSN specifications. Because of the IP core flexibility, Xilinx was able to further improve this performance as the standards matured and add additional functionality that is very much in line with the development of our product and its lifetime.”