The RX IP function block connects the customer’s FPGA logic with the image sensor’s data stream. The core receives the interface data, manages the byte-to-pixel conversion and prepares an efficient processing workflow run on the FPGA. It supports SLVS-EC v1.2 with 1, 2, 4, 8 lanes configurable by the user and delivers pixels formats from 8 to 14-bit of raw data.
The SLVS-EC RX IP Core works with Xilinx’ existing and upcoming FPGA families. The package includes the encrypted RTL IP Core with a ModelSim simulation environment and dedicated reference design examples.
An evaluation kit provides designs for implementation of a SLVS-EC based sensor, including the HW/SW environment and documented implementation examples and source code.