RISC-V-on-FPGA at centre of Microsemi’s Mi-V system: aims to accelerate adoption

October 23, 2017 // By Graham Prophet
Microsemi has configured its Mi-V ecosystem as a program, designed with industry leaders, as an open, low power, programmable RISC-V to increase adoption of its RISC-V soft central processing unit (CPU) product family.

The company also introduced the Mi-V RV32IMA and additional field programmable gate array (FPGA)-based soft CPU solutions, suited for designs utilizing RISC-V open instruction set architectures (ISAs). Microsemi asserts that you can can now select RISC-V for new designs, “knowing a tier one vendor committed to the success of this technology is providing all the necessary tools to confidently use RISC-V soft CPUs.”

 

RISC-V, an ISA which is a standard open architecture under the governance of the RISC-V Foundation, offers portability as well as enabling the open source community to test and improve cores at a faster pace than closed ISAs. As the RISC-V intellectual property (IP) core is not encrypted, it can be used to ensure trust and certifications not possible with closed architectures.

 

Microsemi’s Mi-V ecosystem brings together a number of players involved in the development of RISC-V to simplify RISC-V designs, including Micrium with its uC/OS-II real-time kernel, full-featured embedded operating system; and Express Logic with the X-Ware IoT platform, including ThreadX RTOS.

 

Microsemi’s Mi-V ecosystem, part of Microsemi’s Accelerate Ecosystem, contains a number of components. Design tools include Microsemi’s SoftConsole Eclipse-based integrated development environment (IDE), the firmware catalogue and Libero PolarFire system-on-chip (SoC). Operating systems include Express Logic’s ThreadX, Huawei LiteOS and Micrium µC/OS-II. Boards include the RTG4 development kit, IGLOO2 RISC-V board from Future Electronics, and the PolarFire Evaluation Kit. Debug dongles from Microsemi and Olimex, first-stage bootloaders and soft peripherals are also included. Example projects, drivers and firmware are all available on GitHub.

 

Deployment of soft CPUs implemented with the R11C-V ISA is automatic and delivered to the user’s desktop via Microsemi’s IP Catalog. No end user license agreements are needed to gain access to the soft CPUs. Using RISC-V soft CPUs within the Mi-V ecosystem is free.

 

Microsemi; www.microsemi.com

 

 


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