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Dual Port memory compilers for TSMC 40 nm

Dual Port memory compilers for TSMC 40 nm

By eeNews Europe



ERA is a cost-effective RAM compiler for memories to extend battery life and also reduce silicon area. It is capable of generating instances from 64 bits to 288 kbits, and has a new ultra-low leakage stand-by “NAP” mode. A new add-on, WIPE, allows memory reset in 5 clock cycles.

The ERA compiler is available in single or dual rail with high density, low power, low leakage optimization, in TSMC 40 nm uLP or uLPeF.

More information

www.dolpin-integration.com

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