ERA is a cost-effective RAM compiler for memories to extend battery life and also reduce silicon area. It is capable of generating instances from 64 bits to 288 kbits, and has a new ultra-low leakage stand-by “NAP” mode. A new add-on, WIPE, allows memory reset in 5 clock cycles.
The ERA compiler is available in single or dual rail with high density, low power, low leakage optimization, in TSMC 40 nm uLP or uLPeF.
More information
www.dolpin-integration.com
Related news
ST adds phase-change memory option to BCD processes
ST samples MCU with embedded phase-change memory
Nantero: Memory: The Next Big Opportunity for Differentiated Mobile Devices
Rambus, GigaDevice form ReRAM joint venture
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
eeNews on Google News